In the manufacturing of integrated circuits, patterning techniques such as photolithography and etching are used to form various features such as interconnect structures, source/drain contacts, and the like in device dies on a wafer. As design features in integrated circuits become increasingly downsized (e.g., having smaller critical dimensions), the accuracy of photolithography and etching tools are be challenged. Due to process limitations of photolithography/etching, misalignments may occur during patterning. These misalignments may damage structures near a patterned feature and create device defects, which may negatively affect device performance and yield.